1/9 may 2002 STP5NB100 STP5NB100fp n-channel 1000v - 2.4 w - 5a to-220/to-220fp powermesh? mosfet (*)limited only by maximum temperature allowed (1)i sd 4.7a, di/dt 200a/s, v dd v (br)dss , t j t jmax. internal schematic diagram n typical r ds (on) = 2.4 w n extremely high dv/dt capability n 100% avalanche tested n very low intrinsic capacitances n gate charge minimized description using the latest high voltage mesh overlay ? process, stmicroelectronics has designed an ad- vanced family of power mosfets with outstanding performances. the new patent pending strip layout coupled with the companys proprieraty edge termi- nation structure, gives the lowest r ds(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteris- tics. applications n high current, high speed switching n swith mode power supplies (smps) n dc-ac converters foe welding equipment and uninterruptible power supplies and motor drive absolute maximum ratings (?)pulse width limited by safe operating area type v dss r ds(on) i d STP5NB100 1000 v < 2.7 w 5 a STP5NB100fp 1000 v < 2.7 w 5 a symbol parameter value unit STP5NB100 STP5NB100fp v ds drain-source voltage (v gs = 0) 1000 v v dgr drain-gate voltage (r gs = 20 k w ) 1000 v v gs gate- source voltage 30 v i d drain current (continuos) at t c = 25c 5 5 (*) a i d drain current (continuos) at t c = 100c 3.1 3.1 (*) a i dm ( l ) drain current (pulsed) 15.2 15.2 (*) a p tot total dissipation at t c = 25c 135 40 w derating factor 1.08 0.32 w/c dv/dt (1) peak diode recovery voltage slope 4.5 4.5 v/ns v iso insulation withstand voltage (dc) - 2500 v t stg storage temperature C65 to 150 c t j max. operating junction temperature 150 c 1 2 3 1 2 3 to-220 to-220fp
STP5NB100 - STP5NB100fp 2/9 thermal data avalanche characteristics electrical characteristics (tcase = 25 c unless otherwise specified) off on (1) dynamic to-220 to-220fp rthj-case thermal resistance junction-case max 0.93 3.12 c/w rthj-amb thermal resistance junction-ambient max 62.5 c/w t l maximum lead temperature for soldering purpose 300 c symbol parameter max value unit i ar avalanche current, repetitive or not-repetitive (pulse width limited by t j max) 5a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 220 mj symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 1000 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating 1a v ds = max rating, t c = 125 c 50 a i gss gate-body leakage current (v ds = 0) v gs = 30v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 345v r ds(on) static drain-source on resistance v gs = 10v, i d = 2.5 a 2.4 2.7 w symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds > i d(on) x r ds(on)max, i d = 2.5 a 1.5 s c iss input capacitance v ds = 25v, f = 1 mhz, v gs = 0 1500 pf c oss output capacitance 150 pf c rss reverse transfer capacitance 17 pf
3/9 STP5NB100 - STP5NB100fp safe operating area for to-220fp electrical characteristics (continued) switching on switching off source drain diode note: 1. pulsed: pulse duration = 300 s, duty cycle 1.5 %. 2. pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd = 500 v, i d = 2.5 a r g = 4.7 w v gs = 10 v (see test circuit, figure 3) 24 11 ns ns q g total gate charge v dd = 800v, i d = 5 a, v gs = 10v 39 51 nc q gs gate-source charge 9.6 nc q gd gate-drain charge 19.2 nc symbol parameter test conditions min. typ. max. unit t r(voff) off-voltage rise time v dd = 800v, i d = 5 a, r g =4.7 w, v gs = 10v (see test circuit, figure 5) 20 ns t f fall time 22 ns t c cross-over time 26 ns symbol parameter test conditions min. typ. max. unit i sd source-drain current 5 a i sdm (1) source-drain current (pulsed) 20 a v sd (2) forward on voltage i sd = 5 a, v gs = 0 1.6 v t rr reverse recovery time i sd = 5 a, di/dt = 100a/s, v dd = 100v, t j = 150c (see test circuit, figure 5) 780 ns q rr reverse recovery charge 5.5 c i rrm reverse recovery current 14 a safe operating area for to-220
STP5NB100 - STP5NB100fp 4/9 thermal impedence for to-220 transconductance static drain-source on resistance transfer characteristics output characteristics thermal impedence for to-220fp
STP5NB100 - STP5NB100fp 5/9 source-drain diode forward characteristics normalized gate thereshold voltage vs temp. normalized on resistance vs temperature capacitance variations gate charge vs gate-source voltage
STP5NB100 - STP5NB100fp 6/9 fig. 5: test circuit for inductive load switching and diode recovery times fig. 4: gate charge test circuit fig. 2: unclamped inductive waveform fig. 1: unclamped inductive load test circuit fig. 3: switching times test circuit for resistive load
STP5NB100 - STP5NB100fp 7/9 dim. mm inch min. typ. max. min. typ. max. a 4.40 4.60 0.173 0.181 c 1.23 1.32 0.048 0.051 d 2.40 2.72 0.094 0.107 d1 1.27 0.050 e 0.49 0.70 0.019 0.027 f 0.61 0.88 0.024 0.034 f1 1.14 1.70 0.044 0.067 f2 1.14 1.70 0.044 0.067 g 4.95 5.15 0.194 0.203 g1 2.4 2.7 0.094 0.106 h2 10.0 10.40 0.393 0.409 l2 16.4 0.645 l4 13.0 14.0 0.511 0.551 l5 2.65 2.95 0.104 0.116 l6 15.25 15.75 0.600 0.620 l7 6.2 6.6 0.244 0.260 l9 3.5 3.93 0.137 0.154 dia. 3.75 3.85 0.147 0.151 l6 a c d e d1 f g l7 l2 dia. f1 l5 l4 h2 l9 f2 g1 to-220 mechanical data p011c
STP5NB100 - STP5NB100fp 8/9 l2 a b d e h g l6 f l3 g1 123 f2 f1 l7 l4 l5 dim. mm. inch min. typ max. min. typ. max. a 4.4 4.6 0.173 0.181 b 2.5 2.7 0.098 0.106 d 2.5 2.75 0.098 0.108 e 0.45 0.7 0.017 0.027 f 0.75 1 0.030 0.039 f1 1.15 1.5 0.045 0.067 f2 1.15 1.5 0.045 0.067 g 4.95 5.2 0.195 0.204 g1 2.4 2.7 0.094 0.106 h 10 10.4 0.393 0.409 l2 16 0.630 l3 28.6 30.6 1.126 1.204 l4 9.8 10.6 .0385 0.417 l5 2.9 3.6 0.114 0.141 l6 15.9 16.4 0.626 0.645 l7 9 9.3 0.354 0.366 ? 3 3.2 0.118 0.126 to-220fp mechanical data
9/9 STP5NB100 - STP5NB100fp information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no res ponsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devi ces or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com
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